Data processor with bus-sizing function

ABSTRACT

A data processor capable of controlling memory accessing by the same controls regardless of the bus width to be used. A register is provided for storing data to be inputted and completing a block of data with a size equal to that of the whole bus width of the external data bus when the microprocessor accesses external memory by using only a part of the bus width of an external data bus according to a bus-sizing function. A bus interface is provided for starting memory access by dividing a bus cycle into plural portions according to the bus width and for controlling operation so as to access data equal in size to the case where the whole bus width of the external data bus is used for accessing.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data processor having a bus-sizingfunction, more particularly to a data processor capable of accessingdata buses having bus widths different from each other according to abus-sizing function.

2. Description of Related Art

Some data processors are capable of approximately accessing a memorysystem by switching the effective width of the data bus using abus-sizing function when data is read/written during memory access.

The bus-sizing function includes dynamic bus-sizing and staticbus-sizing. Dynamic bus-sizing as the capability of changing a bus widthby designating a bus width every time memory is accessed. In staticbus-sizing the bus width is fixed to a constant value after designatinga bus width when the whole unit is reset.

In the following, an explanation will given of one example of a ..conventional.!. data processor having a bus-sizing function asmentioned above and also having a cache.

FIG. 1 is a block diagram showing construction of a . .conventional.!.data processor. This data processor is composed of a microprocessor 1and an external memory 6 connected thereto by an external data bus 10and an external address bus 11. Though the bus width of the externaldata bus D (0:63) 10 is 64 bits, using a static bus-sizing function, thebus width can be designated as either 64-bit width or 32-bit width. Inthe case where the external data bus 10 is used in a 32-bit width,accessing is carried out by using only lower 32 bits D (32:63) of theexternal data bus 10. The bit width of the external address bus A (0:31)11 is fixed at a 32-bit width.

The microprocessor 1 is composed of a bus interface 2 and internalfunction circuits. The internal function circuits include an alignmentcircuit 3, a cache memory 4, an internal data operation circuit 5 and soon. Both the alignment circuit 3 and the cache memory 4 are connected tothe bus interface 2 by a D bus 12, which is an internal data bus. Thealignment circuit 3 and the internal data operation circuit 5 areconnected with each other by an S bus 13, while the cache memory 4 andthe alignment circuit 3 are connected with each other by a bus 14.

The data obtained over the external data bus 10 according toread-accessing from the external memory 6 is transferred to thealignment circuit 3 and the cache memory 4 through the bus interface 2and the D bus 12. The read data is registered in the cache memory 4 aswell as aligned by the alignment circuit 3. In the case where the datato be read is registered in the cache memory in advance, the data istransferred to the alignment circuit 3 from the cache memory 4 throughthe bus 14. The data having been aligned by the alignment circuit 3 istransferred to the internal data operation circuit 5 through the S bus13. The respective bus width of the D bus 12, S bus 13 and bus 14 in themicroprocessor 1 is 64 bits.

FIG. 2 is a circuit diagram showing a circuit for a data transferringsystem of the bus interface 2. This circuit is composed of tri-statebuffers 30, 31 and buffers 32, 33. The bus 10H (which is the higher 32bits of the external data bus 10) is connected to the bus 12H (which isthe higher 32 bits of the D bus 12) through the buffer 32 and thetri-state buffer 30, and the bus 10L (which is the lower 32 bits of theexternal data bus 10) is connected to the bus 12L (which is the lower 32bits of the D bus 12) through the buffer 33 and the tri-state buffer 31.

FIG. 3 is a schematic diagram showing logical levels of control signals3A, 3B of the aforementioned tri-state buffers 30, 31 in reading data.In this state, the logical levels of the control signals 3A. 3B arealways "1". Accordingly, data is ouputted from the bus 10H to the bus12H and data is outputted from the bus 10L to the bus 12L.

FIG. 4 is a block diagram showing construction of the alignment circuit3. In the alignment circuit 3, an 88-bit register 400 comprising a 4Aregister 40 of 32 bits, a 4b register 41 of 32 bits, a 4C register 42 of24 bits is provided in order to store non-alignment data inputed fromthe D bus 12. A shifter 43 for aligning data stored in the 88-bitregister 400 and a 64-bit register 44 for preserving data aligned by theshifter 43 are also provided.

The alignment circuit 3 is so constructed as to be able to alignrespective data of 8 bits, 16 bits, 32 bits and 64 bits. 64-bit datacrosses a 32-bit boundary of memory space of the external memory 6 twotimes at most. Therefore 88 bits in total are necessary for the sizes ofthe 4A, 4B, 4C registers 40, 41, 42 storing non-alignment data.

FIG. 5 is a schematic diagram showing how data on the D bus 12 is takeninto the 4A, 4B, 4C registers 40, 41, 42 shown in FIG. 4. The conditionfor the data being taken in is determined by the bus width of theexternal data bus 10 being used and the value of the third bit from thelower side of the address.

FIG. 6 is a block diagram showing a construction of the cache memory 4.The cache memory 4 is composed of a data registering register 50 of 256bits, a data reading register 52, a cache memory data unit 51, a shifter53 taking out 88 bits from 256 bits, a tag registering register 54, acache memory tag unit 55, a tag reading register 56 and so on.

The data registered in one line of the cache memory 4 is 256 bits.External bus access for registering in the cache memory 4 is performedaccording to burst transfer access in which one line of data can beaccessed at high speed. The data registering register 50 is composed ofeight 32-bit registers 5A, 5B . . . 5H. The respective registers 5A, 5B. . . 5H are connected to the bus 12H and to the bus 12L.

FIG. 7 is a schematic diagram showing construction of a part of thememory space to be processed by the microprocessor 1 shown in FIG. 1.Addresses shown in FIG. 7 are byte addresses. The addresses shown inFIG. 7 are the lower 16 bits of 32-bit addresses and are indicated inhexadecimal.

FIG. 8 and FIG. 9 are timing charts showing timings for a burst transferaccess. FIG. 8 shows the case where the external data bus 10 has a64-bit width and FIG. 9 shows the case where it has a 32-bit width,respectively.

Burst transfer access is a transferring method in which four bus cyclesare combined as a set. FIG. 8 and FIG. 9, reference symbol (a)designated clock CLK, (b) data on the external address bus A (0:31). (c)bus start signal #BS, (d) address strobe signal #AS, (e) data strobesignal #DS, and (f) designates a read/write signal R/#W respectively.All of these signals are outputted by the microprocessor 1. Preferencesymbol (g) designates a data-transfer completion signal #DC and (h)designates data on the external data bus D (0:63) 10. These signals areinputted to the microprocessor 1. Further, reference symbol (i)designates an access start signal indicating the start of the bursttransfer access and (j) designates a bus cycle finishing signalindicating an end of each cycle of burst transfer. These signalsindicate the states of the bus cycles to the internal data operationcircuit 5 form the bus interface 2.

Next, an explanation will be given of the operation of such ..conventional.!. data processor as mentioned above.

The microprocessor 1, at first, accesses the built-in cache memory 4when data reading of the memory is necessary. In the case where a cachemiss occurs, that is, where data to be accessed is not stored in thecache memory 4, the bus cycle is started to the external memory 6 toread data by a burst transfer access. When data is read after accessingthe external memory 6, the alignment circuit 3 aligns the data and atthe same time the data is registered in the cache memory 4. The nexttime accessing is performed to the same address, since data is alreadyregistered in the cache memory 4, (that is, since there is a cache hit),the time required for accessing is shortened because there is nonecessity for accessing the external memory 6.

Since the microprocessor 1 has a static bus-sizing function asaforementioned, it can operate by changing the bus width of the externaldata bus 10.

In the following, an explanation will be given of how the operation inthe cache where a cache miss occurs and data is read by a burst transferaccess is different due to various bus widths of the external data bus10 being used.

First an explanation will be given of the case where the external databus 10 is operated with the bus width thereof being 64 bits. At the timethat a cache miss occurs, a burst transfer access is started for readingdata for one line of the cache. Reading data for 256 bits is performedby performing only one burst transfer access, composed of four buscycles with the bus width of the external data bus 10 being 64 bits.

An explanation will now be given of operation for reading data using aburst transfer access in the case where the required first data 701 hasaddresses in the range shown in FIG. 7, (for example, the addressthereof being "000A" and the data length thereof being 64 bits) and acache miss occurs. FIG. 8 is a timing chart of the operation.

At the first cycle of burst transfer access data within the bounds of a64-bit group, in which the first data 701 exists and whose headaddresses is "0008" are accessed. In the following accesses, theremaining data within the bounds of the 256-bit group having the firstdata 701, are successively accessed by wrapping around. Accordingly,burst transfer access is executed in the order of addresses:"0008"→"0010"→"0018"→"0000".

The data given to the external data bus D (0:63) 10 and the D bus 12shown in FIG. 8(h) and FIG. 8(k) are 64-bit data 801, 802, 803, 804, and811, 812, 813, 814, respectively, starting from addresses "0008","0010", "0018", "0000" in order.

The alignment circuit 3 is operated according to the case in FIG. 5where there is a 64-bit data bus width, the third bit from the lowerside of the address being "0". The higher 32 bits of the D bus 12, inthe first cycle accessing the address "0008", are latched by the 4Aregister 40 of the 88 bit register 400, and the lower 32 bits thereofare latched by the 4B register 41 of the same, respectively. The higher32 bits of the D bus 12 in the second cycle accessing the address "0010"are latched by the 4C register 42.

The bus cycle finishing signal shown in FIG. 8(j) indicates thateffective data is on the D bus 12, as well as indicating one end of abus cycle. The data is latched by registers in the alignment circuit 3and the cache memory 4 while the signal is asserted. According to theoperation, the first data 701 is held by the 4A, 4B, 4C registers 40,41, 42 which make up the 88-bit register 400, and the 88-bit data isthen aligned by the shifter 43 and latched by the register 44 to beoutputted to the S bus 13.

In the cache memory 4, the data having been read by a burst transferaccess is latched in order by the data registering register 50. Sincethe addresses to accessed is in order of "0008"→"0010"→"0018"→"0000",the higher 32 bits of the D bus 12 in the first cycle are latched byregister 5C of the data registering register 50, the lower 32 bits arelatched by register 5D, the higher 32 bits of the D bus 12 in the secondcycle are latched by register 5E, the lower 32 bits are latched byregister 5F, the higher 32 bits of the D bus 12 in the third cycle arelatched by register 5G, the lower 32 bits are latched by register 5H,the higher 32 bits of the D bus 12 in the fourth cycle are latched byregister 5A, and the lower 32 bits are latched by register 5B.

Since the bus cycle finishing signal shown in FIG. 8(j) indicates thateffective data is on the D bus 12 as well as indicating the end of a buscycle, the data are latched by each register while the signal isasserted.

When the fourth cycle is finished, the data is registered in the cachememory 4. Accordingly, within the bounds of data the 256-bit groupincluding the first data 701 are registered in the cache.

In the following, an explanation will be given of operation for readingdata according to a burst transfer access in the case where the secondrequired 702 has data addresses in the range shown in FIG. 7, (forexample, the address thereof being "000E" and the data length thereofbeing 64 bits) and a cache miss occurs. In the first cycle of the bursttransfer access, data within the boundary of the 64-bit group in whichthe second data 702 exists and whose address is "0008" are accessed bywrapping around. This case is identical to the case where the first data701 is read. The method for registering in the cache memory 4 is alsothe same. But the operation of the alignment circuit 3 is different.

The alignment circuit 3 is operated according to the case in FIG. 5where there is a 64-bit data bus width and the third bit from the lowerside of the address is "1". The lower 32 bits of the D bus 12 in thefirst cycle accessing the address "0008", are latched by the 4A register40 The higher 32 bits of the D bus 12 of the second cycle accessing theaddress "0010" are latched by the 4B register 41, and the lower 32 bitsare latched by the 4C register 42. According to this operation, thesecond data is held by the 4A, 4B, 4C registers 40, 41, 42 configuringthe 88-bit register 400. The 88-bit data held by the data registeringregister 50 is aligned by the shifter 43 and then latched by theregister 44 to be outputted to the S bus 13.

In the following, an explanation will be given of the case where the buswidth of the external data bus 10 is 32 bits. At the time that a cachemiss occurs, burst transfer accesses are started two times in order toread data for one line of the cache. Two burst transfer accesses, eachcomposed of four bus cycles with the bus width of the external data bus10 being 32 bits, allows a read data of 256 bits.

An explanation will next be given of the operation for reading dataaccording to burst transfer accesses in the case where the first datarequired 701 has addresses in the range shown in FIG. 7 (for example,the address thereof being "000A" and the data length thereof being 64bits), and a cache miss occurs. FIG. 9 is a timing chart showing theoperation.

At the first cycle of the first burst transfer access data within thebounds of the 32-bit group, in which the remaining first data 701 existsand whose head address is "0008", are accessed. In the followingaccesses the remainder of data within the 128-bit group is successivelyaccessed by wrapping around.

At the first cycle of the second burst transfer access, data within thebounds of the 32 bit group, in which the remaining first data exits andwhose head address is "0010", are accessed In the following accesses,the remainder of data within the bounds of the 128 bit group aresuccessively accessed by wrapping around.

Accordingly, the first burst transfer access is performed in the orderof addresses: "0008"→"000C"→"0000"→"0004" and the second burst access isperformed in the order of addresses: "0010"→"0014"→"0018"→"0001C",respectively.

The data 901 through 908 and 911-918 given to the external data bus D(0:63) 10 and D bus 12 shown in FIG. 9(h) and (k), respectively, are32-bit data starting from "0008", "000C", "0000", "0004", "0010","0014", "0018", and "001C". Each of the data 901-908 is on the buses 10Land 12L, i.e., the lower 32-bits of the data buses.

The alignment circuit 3 is operated according to the case in FIG. 7where there is a 32-bit data bus width. The lower 32 bits of the D bus12 in the first cycle of the first burst transfer access where theaddress "0008" is accessed, is latched by the 4A register 40. The lower32 bits of the D bus 12 in the second cycle where the address "000C" isaddressed, are latched by the 4B register 41. The lower 32 bits of the Dbus 12 in the first cycle of the second burst transfer access where theaddress "0010" is accessed, are latched by the 4C register 42.

The bus cycle finish signal shown in FIG. 9(j) indicates that effectivedata is on the D bus 12, as well as indicating the end of a bus cycle.The data is latched by registers in the alignment circuit 3 and thecache memory 4 while this signal is asserted. According to thisoperation, the first data 701 is held by the 4A, 4B, 4C registers 40,41, 42 which make up the 88-bit register 400. This 88-bit data islatched by the register 44 after it is aligned by the shifter 43 to beoutputted to the S bus 13.

In the cache memory 4, the data read during burst transfer access islatched sequentially in the data registering register 50. Since theorder of the addresses to be accessed in the first burst transfer accessis "0008"→"000C"→"0000"→"0004", the lower 32 bits of the D bus 12 in thefirst cycle are latched by register 5C of the data registering register50, the lower 32 bits of the D bus 12 in the second cycle are latched byregister 5D, the lower 32 bits of the D bus 12 in the third cycle arelatched by register 5A, and the lower 32 bits of the D bus 12 in thefourth cycle are latched by register 5B. Since the order of theaddresses to be accessed in the second burst transfer access is"0010"→"0014"→"0018"→"001C" the lower 32 bits of the D bus 12 in thefirst cycle are latched by register 5E of the data registering register50, the lower 32 bits of the D bus 12 in the second cycle are latched byregister 5F, the lower 32 bits of the D bus 12 in the third cycle arelatched by register 5G and the lower 32 bits of the D bus 12 in thefourth cycle are latched by register 5H.

The bus cycle finish signal shown in FIG. 9(j) indicates that effectivedata is on the D bus 12 as well as indicating an end of a bus cycle. Thedata is latched in the register while this signal is asserted.

When the fourth cycle of the second burst transfer access is finished,data is registered in the cache memory 4. Thus, data within the boundsof the 256-bit group, including the first data, 701 is registered in thecache.

An explanation will next be given of the operation in which data is readby a burst transfer access in the cache where required second data 702has addresses in the range shown in FIG. 7, the address thereof being"000E" and the data length thereof being 64 bits and where a cache missoccurs.

At the first cycle of the first burst transfer access data within thebounds of the 32-bit group, in which the first data 701 exists and whosehead address is "000C", is accessed. In the succeeding accesses, theremaining data within the bounds of the 128-bit group having the firstdata 701 are sequentially accessed by wrapping around. Accordingly, thefirst burst transfer access is performed in the order of addresses:"000C"→"0000"→"0004"→"0008". The second burst transfer access is thesame as the case of the first data 701. Since the order of the addressesin the first transfer accessing is different, the operation at thealignment circuit 3 and the operation of registering to the cache memory4 are also different.

The alignment circuit 3 is operated identically to the case where thereis a 32-bit data bus width, shown in FIG. 5. The lower 32 bits of the Dbus 12 during the first cycle of the first burst transfer access, wherethe address "000C" is accessed, is latched by register 4A (40). Thelower 32 bits of the D bus 12 in the second cycle of the second bursttransfer access where the address "0010" is accessed, is latched byregister 4B (41). The lower 32 bits of the D bus 12 during the secondburst transfer access where the address "0014" is accessed, is latchedby register 4C (42).

In the cache memory 4, the data read by burst transfer access issequentially latched in the data registering register 50. Since theorder of the addresses to be accessed in the first transfer access is"000C"→"0000"→"0004"→"0008", the lower 32 bits of the D bus 12 duringthe first cycle are latched by register 5D of the data registeringregister 50, the lower 32 bits of the D bus 12 during the second cycleare latched by register 5A, the lower 32 bits of the D bus 12 during thethird cycle are latched by register 5B, and the lower 32 bits of the Dbus 12 during the fourth cycle are latched by register 5C. Since theorder of the addresses to be accessed in the second burst transferaccessing is "0010"→"0014"→"0018"→"001C", the lower 32 bits of the D bus12 during the first cycle are latched by register 5E of the dataregistering register 50, the lower 32 bits of the D bus 12 during thesecond cycle are latched by register 5F, the lower 32 bits of the D bus12 during the third cycle are latched by register 5G, and the lower 32bits of the D bus 12 during the fourth cycle are latched by register 5H.

When the fourth cycle of the second burst transfer access is finished,data is registered in the cache memory 4. Thus, data which is within thebounds of the 256-bit group including the second data 702 are registeredin the cache.

In the . .conventional.!. data processor, the controlling method of theinternal function circuits such as alignment circuit, cache memory, andinternal data operation circuit, is changed to correspond to the buswidth of the external data bus (which can be changed according to thestatic bus-sizing function). And, as aforementioned, in order to readonly the data required for registering to the cache memory, the dataprocessor is so operated as to change the number of times burst transferaccess is performed, responsive to the bus width of the external databus. The internal data operation circuit transmits addresses to the businterface to request accessing. The internal data operation circuit,however, so controls as to request only one access when the bus width ofthe external data bus to be used is 64 bits and to request two accesseswhen the bus width thereof is 32 bits.

Accordingly, in the . .conventional.!. data processor, it is necessaryfor the internal function circuit of the microprocessor to be operatedunder the control of different procedures corresponding to the bus widthof the external data bus indicated by the bus-sizing function. Becauseof this, the internal function circuit is complicated.

SUMMARY OF THE INVENTION

The present invention has been devised in order to solve such problemsand the object thereof is to provide a data processor in which theinternal function circuit of the microprocessor can be operated underthe same control regardless of the width of the data bus.

The data processor of the invention is provided with a microprocessor,an external data bus, and an external memory connected to themicroprocessor through the external data bus. The memory area has aplurality of memory boundaries defining units equal to the whole widthof the bus. The data processor is further provided with a bus-sizingmeans which, when accessing the external memory to the microprocessor,switches between a state of using a part of the bus width of theexternal data bus to a state of using all of the bus width. The dataprocessor includes accessing means for accessing a plurality ofcontinuous bounded memory units including an address to be accessed, inthe case where data at the optional position on the external memory isaccessed. The data processor includes address generating means forgenerating a head address of the bounded memory unit including theaddress on the basis of the address to be accessed, and with a businterface circuit for continuously accessing, in order, the data withinthe bounds of a memory area from the head address generated by theaddress generating means.

In addition to the aforesaid configuration, the data processor of theinvention is provided with an internal data bus having, inside themicroprocessor, the same bit width as the external data bus and intowhich data is inputted from the external data bus, and with a registerof the same bit width as the bus width except the minimum which can bedesignated by the bus-sizing means. The data processor is so constructedthat the bus interface circuit outputs the data on the external data busdirectly to the internal data bus at every access in the case where theexternal memory is continuously accessed using the whole bus width ofthe external data bus. The data processor stores data from the externaldata bus into the register at every access in the case where theexternal memory is continuously accessed using a part of the bus widthof the external data bus. In next access, the data processor outputs thedata from the external data bus to the corresponding bit position of theinternal data bus (in the case where the register is filled with data)as well as outputs the data stored in the register to the correspondingbit position of the internal data bus.

Further, the data processor of the invention comprises a microprocessor,an external data bus, and an external memory connected to themicroprocessor through the external data bus and is provided, in themicroprocessor, with bus-sizing means which switches between a stateusing a part of the bus width of the external data bus in accessing theexternal memory to and a state using the whole bus width. The dataprocessor includes accessing means for accessing the external memorycontinuously by processing a predetermined number of accesses of theexternal bus as a set, and a bus interface circuit starting an externalbus access to the external memory by receiving a request for an accessstart in the case where an access start is requested. The bus interfacecircuit is so composed as to access the memory area corresponding to theexternal memory. The means for accessing generates a set of continuousexternal bus accesses in the case where the whole bus width of theexternal data bus is used to request an access start, and to accesssuccessively the memory area in the case where the whole bus width ofthe external data bus is used, by generating a plurality of continuousexternal bus accesses responsive to the bus width to be used. The meansfor accessing generates an address for the first external bus access ofthe external bus accesses of each set in the case where a part of thebus width of the external data bus is used, thereby starting continuousexternal bus accesses of each set.

In the data processor of the invention, a plurality of continuousbounded areas of memory are accessed by the accessing means from thebounded memory area including an address to be accessed (in the casewhere data on an optional position of the external memory is accessed),and at this time, a head address of the memory boundary including theaddress is generated by the address generating means on the basis of theaddress to be accessed. From the head address generated by the addressgenerating means, the remainder of the data within the bounded memoryarea is successively accessed by the bus interface circuit.

And in the data processor of the invention, the data inputted form theexternal data bus is stored in the register in the case where only apart of bus width of the external data bus is used. The data inputtedfrom the external data bus is outputted intact to the internal data busin the case where the data stored in this register and the data inputtedfrom the external data bus are outputted to the internal data bus andthe whole width of the external data bus is used.

Further, in the data processor of the invention, the memory areacorresponding to the external memory is accessed by generating a set ofcontinuous external bus accesses in the case where accessing isperformed by using the whole bus width of the external data bus inresponse to a request for an access start by the bus interface circuit.The memory area in the case where the whole bus width of the externaldata bus is used, is successively accessed by generating a plurality ofcontinuous external bus accesses corresponding to the bus width to beused. In the case where a part of the bus width of the external data busis used, the memory area is accessed by generating an address for thefirst external bus access of the continuous external bus accesses ofeach set, thereby starting the continuous external bus accesses of eachset.

The above and further objects and features of the invention will morefully be apparent from the following detailed description withaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a data processor ..of conventional design, also.!. applicable to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a circuit for adata transfer system of a bus interface of a . .conventional.!. dataprocessor.

FIG. 3 is a schematic diagram showing logical levels of a control signalfor a tri-state buffer of a data transfer system of a bus interface atthe time of reading data.

FIG. 4 is a block diagram showing a configuration of an alignmentcircuit of a data processor . .of conventional design and also.!.applicable to the present invention.

FIG. 5 is a schematic diagram showing how data on D bus is taken intoregisters 4A, 4B and 4C of an alignment circuit shown in FIG. 4.

FIG. 6 is a block diagram showing a configuration of a cache memory of adata processor . .of conventional design and also.!. applicable to thepresent invention.

FIG. 7 is a schematic diagram showing a configuration of a part of amemory space.

FIG. 8 is a timing chart showing timing for a burst transfer access inthe case where the data bus has a 64-bit width in a data processor . .ofconventional design and also.!. applicable to the present invention.

FIG. 9 is a timing chart showing timing for a burst transfer access inthe case where the data bus has a 32-bit width in a . .conventional.!.data processor.

FIG. 10 is a circuit diagram showing a configuration of a circuit for adata transfer system of a bus interface of a data processor according tothe present invention.

FIG. 11 is a schematic diagram showing logical levels of a tri-statebuffer control signal of a circuit for a data transfer system of a businterface at the time of reading data.

FIG. 12 is a timing chart showing timing for a burst transfer access inthe case where the data bus has a 32-bit width in a data processoraccording to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, an explanation will be given of the invention,referring to drawings showing embodiments thereof. In addition, in eachdrawing which is referred to when explanation is made on the presentinvention, the same reference symbols as in each drawing of theaforesaid conventional example show either the same or correspondingparts.

FIG. 1 is a block diagram showing an example of a configuration of thedata processor of the present invention, and it shows a sameconfiguration as the conventional data processor including the fact thatit has a bus-sizing function except that the circuit for data transferof the bus interface 2 is as shown in FIG. 10.

The data processor of the invention is composed of a microprocessor 1and an external memory 6 connected with the microprocessor 1 by theexternal data bus 10 and the external address bus 11. Though the buswidth of the external data bus D (0:63) 10 is 64 bits, it has a staticbus-sizing function which can designate the bus width of the externaldata bus 10 as either 64-bit width or 32-bit width. When the externaldata bus is used in a 32-bit configuration, only the lower 32 bits D(32:63) of the external data bus 10 is used for access. The bus width ofthe external address bus A (0:31) 11 is fixed to a 32-bit width.

The microprocessor 1 is composed of the bus interface 2 and the internalfunction circuit. The internal function circuit, includes the alignmentcircuit 3, cache memory 4, internal data operation circuit 5 and so on.Both the alignment circuit 3 and the cache memory 4 are connected to thebus interface 2 by the D bus 12 which is an internal data bus. Thealignment circuit 3 and the internal data operation circuit 5 areconnected by the S bus 13. The cache memory 4 and the alignment circuit3 are connected by bus 14.

FIG. 10 is a circuit diagram showing a configuration of the circuit forthe data transfer system of the bus interface 2. This circuit iscomposed of tri-state buffers 20, 21, 22 and 32-bit register 23, andbuffers 24, 25. A bus 10H (which is the higher 32 bits of the externaldata bus 10) is connected to a bus 12H (which is the higher 32 bits ofthe D bus 12) through the buffer 24 and the tri-state buffer 20, and abus 10L (which is the lower 32 bits of the external data bus 10) isconnected to a bus 12L (which is the lower 32 bits of the D bus 12)through the buffer 25 and tri-state buffer 22. In addition, the outputof the buffer 25 is also connected to the register 23, and the output ofthis register 23 is connected to the bus 12H through the tri-statebuffer 21.

The configurations of the alignment circuit 3 and the cache memory 4 arethe same as those of . .conventional.!. design shown in FIG. 4 and FIG.6, respectively.

In FIG. 11, logical levels of the control signals 2A, 2B, 2C of thetri-state buffers 20, 21, 22 in reading data are shown. The controlsignals 2A, 2B, 2C are changed responsive to the bus width of theexternal data bus 10. In the case where the external data bus 10 has a64-bit bus width, the higher 32 bits of the external data bus 10 areoutputted to the higher 32 bits of the D bus 12, and the lower 32 bitsof the external data bus 10 are outputted to the lower 32 bits of the Dbus 12. In the case where the external data bus 10 has a 32-bit buswidth, data of the register 23 is outputted to the higher 32 bits of theD bus 12 and the lower 32 bits of the external data bus 10 is outputtedto the lower 32 bits of the D bus 12.

FIG. 7 is a schematic diagram showing a configuration of a part of thememory space of the external memory 6, being the same as that of the ..conventional.!. example. Addresses shown in FIG. 7 are byte addresses,and what is shown here are the lower 16 bits of 32 bits addresses. Theseare shown as hexadecimal numbers.

FIG. 8 and FIG. 12 are timing charts showing timing for a burst transferaccess. FIG. 8 shows the case where the external data bus 10 has 64-bitwidth, being the same as the case of 32-bit bus width. FIG. 12 shows thecase of 32-bits bus width.

Next, an explanation will be given of the operation of the dataprocessor of the invention, referring to the drawings.

The microprocessor 1 accesses the built-in cache memory 4 when it isnecessary to read data to a memory. When a cache miss occurs, that is,when the data to be accessed is not stored in the cache memory 4 inadvance, a bus cycle is stored to the external memory 6. Data is thenread according to a burst transfer access. When the external memory isaccessed to read data, the alignment circuit 3 aligns the data, and atthe same time the data is registered in the cache memory 4. The nexttime the same address is accessed, since the data already exists in thecache memory 4 (i.e., there is a cache hit), the time required foraccessing is shortened.

The data processor of the invention can be operated even when the buswidth of the external data bus 10 is changed since it has a staticbus-sizing function.

An explanation will be given, in the following, of how operation in thecase where a cache miss occurs and data is read according to a bursttransfer access due to various bus widths of the external data bus 10being used.

At first, the case where the external data bus 10 has a 64-bit bus widthis almost the same as that of the conventional example.

The circuit for the data transfer system of the bus interface 2 of theinvention (shown in FIG. 10), in the case where the external data bus 10has a 64-bit bus width, outputs the higher 32 bits of the external databus 10 to the higher 32 bits of the D bus 12, and the lower 32 bits ofthe external data bus 10 to the lower 32 bits of the D bus 12,respectively. Accordingly, the operation thereof is same as that of thecircuit for the data transferring system of the . .conventional.!. databus interface 2 shown in FIG. 2.

A request for an access start to the first data of the address in therange shown in FIG. 7 is provided to the bus interface 2 by the internaldata operation circuit 5 only one time. At this time, the head address"000A" of the first data 701 is sent to the bus interface 2. Judgingfrom the fact that the external data bus 10 has a 64-bit bus width, thebus interface 2 starts one block transfer access.

The bus cycle finish signal shown in FIG. 8(j) indicated in the presentinvention, is not an end of a bus cycle but indicates that there iseffective data on the D bus 12. But in the case where the external databus 10 has a 64-bit bus width, it coincides with the end of a bus cycle.

Next, an explanation will be given of the case where the external databus 10 has a 32-bit bus width. At the time of a cache miss, twoinstances of burst transfer accesses are started for reading data forone line of the cache. When the bus width of the external data bus 10 is32 bits, 256 bits of data can be read using two instances of bursttransfer access, each composed of a set of four bus cycles.

An explanation will next be given of the case where data is readaccording to a burst transfer access, where the required first data 701has addresses in the range shown in FIG. 7, the address thereof being"000A" and the data length thereof being 64 bits, and when a cache missoccurs. FIG. 12 is a timing chart showing this operation.

A request for an access start to the first data 701 is provided to thebus interface 2 only one time by the internal data operation circuit 5.At this time, the head address "000A" of the first data 701 is sent tothe bus interface 2. Judging from the fact that the external data bus 10has a 32-bit bus width, the bus interface 2 automatically starts twoinstances of block transfer access in response to one request for anaccess start from the internal data operation circuit 5. The businterface 2 also generates automatically a head address of the secondburst transferring access. The first burst transfer access starts fromthe address ""000A" and the second burst transfer access starts fromaddress "0010".

At the first cycle of the first burst transfer access data within thebounds of the 32-bit group in which the first data 701 exists and whosehead address is "0008", is accessed. In the successive accesses, theremaining data within the bounds of the 128-bit group having the firstdata 701 are accessed successively by wrapping around. At the firstcycle of the second burst transfer access data within the bounds of the32-bit group, in which the remaining first data 701 is exists and whosehead address is "0010", is accessed. In the successive accesses, theremaining data within the bounds of the 128-bit group having the firstdata 701 is successively accessed by wrapping around.

Accordingly, in the first burst transfer access, accessing is performedin the order of addresses. "0008"→"000C"→"0000"→"0004". In the secondburst transfer access, accessing is performed in the order of addresses:"0010"→"0014"→"0018"→"001C", respectively.

In the case where the external data bus 10 has a 32-bit bus width, thecircuit for the data transfer system of the interface 2 of the invention(shown in FIG. 10) outputs the data in register 23 to the higher 32 bitsof the D bus 12 and outputs the lower 32 bits of the external data bus10 to the lower 32 bits of the D bus 12. The data having been read at anodd-numbered cycle of the burst transfer access is latched in register23. At even-numbered cycles of the burst transfer access, since the dataon the register 23 is outputted to the higher 32 bits of the D bus 12and the lower 32 bits of the external data bus 10 is outputted to thelower 32 bits of the D bus 12, respectively, the data having been readat oddnumbered cycles immediately before the even-numbered cycles andthe data having been read at an even-numbered cycle make up 64 bits tobe outputted to the D bus 12.

Data 1201 through 1208 given to the external data bus D (32:63) 10 shownin FIG. 12(h) is 32-bit data starting from "0008", "000C", "0000","0004", "0010", "0014", "0018", and "001C" in order. The data is on thelower 32 bits of the external data bus 10.

The data 1211, 1213, 1215, 1217 given to the D bus 12 shown in FIG.12(K) are 64-bit data starting from "0008", "0000", "0010", and "0018"in order, that is, concatenated data of above-mentioned data 1201 and1202, data 1203 and 1204, data 1205 and 1206, and data 1207 and 1208,respectively.

The bus cycle finish signal in the microprocessor 1 shown in FIG. 12(j)indicates not the end of a bus cycle but also indicates that effectivedata is on the D bus 12.

Accordingly, the data is latched to registers of the alignment circuit 3and the cache memory 4 while this signal is asserted.

From the viewpoint of the alignment circuit 3 and the cache memory 4,the fact that two burst transfer accesses have been performed is notrecognized, and the operations of the alignment circuit 3 and cachememory 4 are the same as the case where 64-bit data is read in the orderof addresses: "0008"→"0000"→"0010"→"0018". Where the external data bus10 has a 32-bit bus width, even though sometimes there may be a casewhere an address does not wrap around, there is no problem since thealignment circuit 3 and the cache memory 4 latched data to each registerafter seeing an address from the 32-nd bit from the lower side to 5-thbit.

The alignment circuit 3 is operated according to the case, shown in FIG.5, where there is a 64-bit data bus width, and the third bit from thelower side is "0". The operation of the microprocessor 1 is onlydifferent according to a value of the 3rd bit from the lower side of anaddress, since the alignment circuit 3 is capable of operatingregardless of the bus width of the external data bus 10. The higher 32bits on the D bus 12 when the first bus cycle finish signal iseffective, (being equivalent to the case where 64 bits are accessed fromaddress "0008"), are latched to the 4A register 40 and the lower 32 bitsare latched to the 4B register 41, respectively. The higher 32 bits onthe D bus 12 when the third bus cycle finish signal is effective, beingequivalent to the case where 64 bits are accessed from address "0010",are latched to the 4C register 42. According to the operation, the firstdata 701 is stored in the 4A, 4B, 4C registers 40, 41, 42 making up the88-bit register 400, respectively. The 88-bit data is aligned by theshifter 43 and latched to the register 44 to be outputted to the S bus13.

In the cache memory 4, the data having been read according to a bursttransfer access is successively latched in the data registering register50. Since the case where addresses are in the order:("0008"→"0000"→"0010"→"0018" is equivalent to the case where data isread 64 bits at a time, the higher 32 bits on the D bus 12 when thefirst bus cycle finish signal is effective, (being equivalent to thecase where 64 bits are accessed from address "0008"), are latched byregister 5C of the data registering register 50, and the lower 32 bitsare latched by register 5D. The higher 32 bits on the D bus 12 when thesecond bus cycle finish signal is effective, (being equivalent to thecase where 64 bits are accessed from address "0000"), are latched byregister 5A, and the lower 32 bits are latched by register 5B. Thehigher 32 bits on the D bus 12 when the third bus cycle finish signal iseffective, (being equivalent to the case where 64 bits are accessed fromaddress "0010"), are latched by register 5E, and the lower 32 bits arelatched by register 5F. The higher 32 bits on the D bus 12 when thefourth bus cycle finish signal is effective, (being equal to the casewhere 64 bits are accessed from address "0018") are latched by register5G, and the lower 32 bits are latched by register 5H.

When the fourth bus cycle finish signal becomes effective and all theaccesses are finished, data is registered in the cache memory 4. Thus,256 bits of data including the first data 701 is registered in thecache.

An explanation will now be given of operations in the case where data isread according to a burst transfer access, where second data 702 havingaddresses in the range shown in FIG. 7, (here the address thereof being"000E" and the data length thereof being 64 bits) is required and acache miss occurs.

A request for an access start to the second data 702 is provided to thebus interface 2 only one time by the internal data operation circuit S.At this time, the head address "000E" of the second data 702 is sent tothe bus interface 2. Judging from the fact that the internal data bus 10has a 32-bit bus width, the bus interface 2 automatically starts twoinstances of burst transfer access in response to one request for anaccess start from the internal data operation circuit 5. The businterface 2 also generates a head address of the second burst transferaccess automatically. The first burst transfer access starts fromaddress "000E" and the second burst transfer accessing starts fromaddress "0010".

At the first cycle of the first burst transfer access 32 bits areaccessed from the head address "0008" of the 64-bit group at which thedata 702 exists. In the successive accesses, the remaining of datawithin the bounds of the 128-bit group having the second data 702 issuccessively accessed by wrapping around.

At the first cycle of the second burst transfer access, 32 bits wherethe remaining data 701 exists and whose head address is "0010", areaccessed. In the successive accesses remaining within the bounds of the128-bit group having the first data 701 is successively accessed bywrapping around.

Accordingly, the addresses are accessed in the order:"0008"→"000C"→"0000"→"0004", and in the second burst transfer access,the addresses are accessed in the order: "0010"→"0014"→"0018"→"001C",respectively.

From the viewpoint of the alignment circuit 3 and the cache memory 4,the fact that two burst transfer accesses are carried out is notrecognized, and the operations of the alignment circuit. 3 and cachememory 4 are the same as the case where 64-bit data is read in theorder: "0008"→"0000"→"0010"→"0018".

The alignment circuit 3 is operated according to the case, shown in FIG.5, where there is a 64-bit data bus width and the third bit from thelower side of the addresses is "1". In the present invention, since thealignment circuit 3 is capable of operating regardless of the bus of theexternal data bus 10, the operation is only different according to thevalue of the third bit from the lower side of an address. The lower 32bits on the D bus 12 when the first bus cycle finish signal iseffective, (being equivalent to the case where 64 bits are accessed fromaddress "0008"), is latched to the 4A register 40. The higher 32 bits onthe D bus 12 when the third bus cycle finish signal becomes effective,(being equivalent to the case where 64 bits are accessed from address"0010"), is latched to the 4B register 41, and the lower 32 bits arelatched to the 4C register 42. According to this operation, the seconddata 702 is stored in the A4. 4B, 4C registers 40, 41, 42 which make upthe 88-bit register 400. The 88-bit data is aligned by the shifter 43and latched to the register 44, to be outputted to the S bus 13.

The operation of the cache memory 4 in the case where the second data702 is accessed becomes identical to that in the case where the firstdata 701 is accessed.

In the embodiment as aforementioned, in bus accessing by using a part ofa bus width of an external data bus according to a bus-sizing function,there is provided a bus interface with a register for storing datasuccessively inputted from the external data bus and for aligning datafor the bus width of the external data bus, a circuit for generating asignal which indicates that the data aligned by using the register isbeing outputted on the internal data bus, and a circuit capable ofperforming an access request of one data bus, starting bus accessingafter dividing a bus cycle in two, according to the bus width and byaccessing an amount of data which can be input or output with an accesswhich uses all of the external data bus.

In the aforementioned embodiment, a protocol is provided fortransmitting/receiving a request for an access start from internalfunction circuits to a bus interface, or transmitting/receiving data,bus cycle signals and so on from the bus interface to the internalfunction circuits, wherein the case where a part of the external databus is used, can be equivalent to the case where the whole of theexternal data bus is used.

As described in the above, according to the data processor of theinvention, since a protocol for transmitting/receiving data and signalbetween a bus interface and internal function circuits are constructedso that it can be controlled with same protocol regardless of the buswidth of the external data bus, the constructions of the internalfunction circuit and its control circuit can be simplified.

As this invention may be embodied in several forms without departingfrom the spirit of essential characteristics thereof, the presentembodiment is therefore illustrative and not restrictive, since thescope of the invention is defined by the appended claims rather than bydescription preceding them, and all changes that fall within the meetsand bounds of the claims, or equivalents of such meets and boundsthereof are therefore intended to be embraced by the claim.

What is claimed is:
 1. A data processor comprising a microprocessor, anexternal data bus having a variable n-byte width, wherein n is an eveninteger and an external memory which is connected with saidmicroprocessor through said external data bus and whose memory area iscomposed of a plurality of memory boundaries defined by n-bytes as oneunit, wherein said microprocessor is provided with:bus-size switchingmeans for switching between a first case of using said external data busin n-bytes width and a second case of using said external data bus inn/2 byte width when accessing said external memory; accessing means for,in said first case, successively accessing m memory boundaries, whereinm is an even integer, including a memory boundary where an address to beaccessed exists by wrapping around from said memory boundary where anaddress to be accessed exists, and in said second case, successivelyaccessing m/2 memory boundaries including a memory boundary where anaddress to be accessed exists by wrapping around from said memoryboundary where an address to be accessed exists; address generatingmeans for generating a head address of said memory boundary of n-byteunits, said n-byte units including said address to be accessed; and abus interface circuit for accessing successively the inside of saidmemory area in an order from the head address of addresses generated bysaid address generating means.
 2. A data processor as set forth in claim1, wherein said microprocessor is further provided with:an internal databus having n-byte width and to which data is inputted from said externaldata bus, and a register having n-byte width which connects saidexternal data bus with said internal data bus, and said bus interfacecircuit, when said external memory is successively accessed by using theentire n-byte bus width of said external data bus, outputs data ofn-bytes on said external data bus directly to said internal data bus atevery access, in the absence of using said register and when saidexternal memory is successively accessed by using n/2 byte bus width ofsaid external data bus, stores data of n/2 bytes from said external databus into said register at every time of accessing, and outputs data ofn/2 bytes stored in said register to bit positions corresponding to saidinternal data bus and outputs data of n-bytes on said internal data busby outputting data of n/2 bytes to bit positions corresponding to saidinternal data bus from said external data bus at every even numberedaccess.
 3. The data processor of claim 1 where n=8 and m=4.
 4. A dataprocessor comprising a microprocessor, an external data bus having a buswidth, and an external memory which is connected with saidmicroprocessor, whereinsaid microprocessor is provided with:bus-sizingmeans for switching between a state of using a part of the bus width ofsaid external data bus and a state of using all of said bus width foraccessing said external memory; accessing means for accessing saidexternal memory successively by executing a predetermined number ofexternal bus accesses as a set, and a bus interface circuit for,receiving a request for an access start and starting an external busaccess to said external memory; and wherein said bus interface circuit,in response to a single request for an access startwhen all of said buswidth of said external data bus is used, generates a single set ofsuccessive external bus accesses, and when a part of the bus width ofthe external data bus is used, generates a plurality of sets ofsuccessive external bus accesses, starts each set of successive externalbus accessing by generating addresses for the first external bus accessof each set of successive external bus accesses, and accessessuccessively a memory area of the same size as in the case where all ofsaid bus width of said external data bus is used.
 5. A method foraccessing memory in a data processor, said data processor having amicroprocessor, means for storing a block of data, an external data bushaving an effective bus width selectable between n-bytes and n/2 bytes,wherein n is an even integer and an external memory which is connectedto said microprocessor through said external data bus, said externalmemory having a plurality of addressable memory locations each having awidth of n-bytes, the method comprising the steps of:selecting whethersaid effective bus width of said external data bus is to be n-bytes orn/2 bytes; generating, in said microprocessor, an access request toaccess a specific addressable memory location in said external memory;generating, in an address generating circuit, a head address of a blockof data to be accessed, wherein said head address is generated based onsaid specific addressable memory location; accessing said externalmemory, wherein said accessing is accomplished in a series of accessessufficient to retrieve a block of data; generating a bus transferfinishing signal upon completion of each of said series of accesses;transferring said block of data through an internal data bus, saidinternal data bus having a bus width equal to n-bytes; storing saidblock of data, wherein said storing is accomplished in a certain orderif said external bus width is n-bytes, and is accomplished in the sameorder if said external bus width is n/2 bytes; transferring said blockof data to said means for storing.
 6. The method of claim 5, whereinsaid step of transferring said block of data . .to said alignmentregister.!. .Iadd.through said internal bus .Iaddend.further comprisesproviding an n.Iadd./2.Iaddend.-byte wide register between said externaldata bus and said internal data bus.
 7. The method of claim 6, whereinsaid external data bus is selected to be n-bytes wide, wherein said stepof transferring said block of data . .to an alignment register.!..Iadd.through said internal bus .Iaddend.further comprises the stepof:passing data from said external bus directly to said internal buswithout passing through said n.Iadd./2.Iaddend.-byte wide register. 8.The method of claim 6, wherein said external data bus is selected to ben/2 bytes wide, wherein said step of transferring said block of data ..to an alignment register.!. .Iadd.through said internal bus.Iaddend.further comprises the step of:passing n/2 bytes of data fromsaid external data bus to said n.Iadd./2.Iaddend.-byte register in eachof said series of transfers; passing n-bytes of data . .to saidalignment register.!. .Iadd.through said internal bus .Iaddend.in everyeven-numbered transfer of said series of transfers.
 9. The method ofclaim 5 wherein said means for storing is a cache.
 10. The method ofclaim 5 wherein said step of transferring said block of data through aninternal data bus further comprises the step of transferring said blockof data to an alignment register.
 11. A method, for accessing memory ina data processor, said data processor having a microprocessor, means forstoring a block of data, an external data bus having an effective buswidth selectable between n-bytes and n/2 bytes, wherein said n is 8 andwherein said block of data is 256 bits wide said data processor havingan external memory which is connected to said microprocessor throughsaid external data bus, said external memory having a plurality ofaddressable memory locations each having a width of n-bytes, the methodcomprising the steps of:selecting whether said effective bus width ofsaid external data bus is to be n-bytes of n/2 bytes; generating, insaid microprocessor, an access request to access a specific addressablememory location in said external memory; generating, in an addressgenerating circuit, a head address of a block of data to be accessed,wherein said head address is generated based on said specificaddressable memory location; accessing said external memory, whereinsaid accessing is accomplished in a series of accesses sufficient toretrieve a block of data; generating a bus transfer finishing signalupon completion of each or said series of accesses; transferring saidblock of data through an internal data bus, said internal data bushaving a bus width equal to n-bytes; storing said block of data, whereinsaid storing is accomplished in a certain order if said external buswidth is n-bytes, and is accomplished in the same order if said externalbus width is n/2 bytes; transferring said block of data to said meansfor storing.
 12. The method of claim 11 wherein said means for storingis a cache.
 13. The method of claim 11 wherein said step of transferringsaid block of data through an internal data bus further comprises thestep of transferring said block of data to an alignment register. .Iadd.14. A data processor comprising a microprocessor, an external data bushaving a variable n-byte width, wherein n is an even integer, and anexternal memory which is connected to said microprocessor through saidexternal data bus and whose memory area is composed of a plurality ofmemory boundaries defined by at least one addressable memory location asone unit, wherein said data processor is provided with;bus-sizeswitching means for switching between a first case of using saidexternal data bus in n-bytes width and a second case of using saidexternal bus in n/2 byte width when accessing said external memory;accessing means for, in said first case, successively accessing aplurality of memory boundaries, including a memory boundary where anaddress to be accessed exists by wrapping around from said memoryboundary where an address to be accessed exists, and successivelyproviding n-byte units derived therefrom to said external bus, and insaid second case, successively accessing a plurality of memoryboundaries including a memory boundary where an address to be accessedexists by wrapping around from said memory boundary where an address tobe accessed exists, and successively providing n/2-byte units derivedtherefrom to said external bus; address generating means for generatinga head address of said memory boundary where said address to be accessedexists; and a bus interface circuit for accessing successively theinside of said memory area in an order from the head address ofaddresses generated by said address generating means. .Iaddend..Iadd.15.A data processor comprising a microprocessor, an external data bushaving a variable n-byte width, wherein n is an even integer and anexternal memory which is connected to said microprocessor through saidexternal data bus and whose memory area is composed of a plurality ofmemory boundaries defined by at least one addressable memory location asone unit, wherein said data processor is provided with; bus-sizeswitching circuitry for switching between a first case of using saidexternal data bus in n-bytes width and a second case of using saidexternal bus in n/2 byte width when accessing said external memory;accessing circuitry for, in said first case, successively accessing aplurality of memory boundaries, including a memory boundary where anaddress to be accessed exists by wrapping around from said memoryboundary where an address to be accessed exists, and successivelyproviding n-byte units derived therefrom to said external bus, and insaid second case, successively accessing a plurality of memoryboundaries including a memory boundary where an address to be accessedexists by wrapping around from said memory boundary where an address tobe accessed exists, and successively providing n/2-byte units derivedtherefrom to said external bus; address generating circuitry forgenerating a head address of said memory boundary where said address tobe accessed exists; and a bus interface circuit for accessingsuccessively the inside of said memory area in an order from the headaddress of addresses generated by said address generating means..Iaddend..Iadd.16. A data processor comprising a microprocessor, anexternal data bus having a variable n-byte width, wherein n is an eveninteger and an external memory which is connected to said microprocessorthrough said external data bus and whose memory area is composed of aplurality of n-byte memory boundaries defined by n-bytes as one unit,each of said n-byte units having an upper half and a lower half, whereinsaid data processor is provided with;bus-size switching means forswitching between a first case of using said external data bus inn-bytes width and a second case of using said external bus in n/2 bytewidth when accessing said external memory; accessing means for, in saidfirst case, successively accessing a plurality of memory boundaries,including a memory boundary where an address to be accessed exists, bywrapping around from said memory boundary where an address to beaccessed exists, and successively providing n-byte units derivedtherefrom to said external bus, and in said second case, successivelyaccessing a plurality of memory boundaries, including a memory boundarywhere an address to be accessed exists, by wrapping around from saidmemory boundary where an address to be accessed exists, and successivelyproviding n/2-byte units derived therefrom to said external bus; addressgenerating means for generating a head address of said memory boundarywhere said address to be accessed exists, which head address is on ann-byte memory boundary, both in the case in which the address to beaccessed is within the upper half of the n-byte unit beginning at saidmemory boundary, and the case in which the address to be accessed iswithin the lower half of said n-byte unit; and a bus interface circuitfor accessing successively the inside of said memory area in an orderfrom the head address of addresses generated by said address generatingmeans. .Iaddend..Iadd.17. A data processor comprising a microprocessor,an external data bus having a variable n-byte width, wherein n is aneven integer, and an external memory which is connected to saidmicroprocessor through said external data bus and whose memory area iscomposed of a plurality of n-byte memory boundaries defined by n-bytesas one unit, each of said n-byte units having an upper half and a lowerhalf, wherein said data processor is provided with: bus-size switchingcircuitry for switching between a first case of using said external databus in n-bytes width and a second case of using said external bus in n/2byte width when accessing said external memory; accessing circuitry for,in said first case, successively accessing a plurality of memoryboundaries, including a memory boundary where an address to be accessedexists, by wrapping around from said memory boundary where an address tobe accessed exists, and successively providing n-byte units derivedtherefrom to said external bus, and in said second case, successivelyaccessing a plurality of memory boundaries, including a memory boundarywhere an address to be accessed exists, by wrapping around from saidmemory boundary where an address to be accessed exists, and successivelyproviding n/2-byte units derived therefrom to said external bus; addressgenerating circuitry for generating a head address of said memoryboundary where said address to be accessed exists, which head address ison an n-byte memory boundary, both in the case in which the address tobe accessed is within the upper half of the n-byte unit beginning atsaid memory boundary, and the case in which the address to be accessedis within the lower half of said n-byte unit; and a bus interfacecircuit for accessing successively the inside of said memory area in anorder from the head address of addresses generated by said addressgenerating circuitry. .Iaddend..Iadd.18. A data processor comprising amicroprocessor, an external data bus having a variable n-byte width,wherein n is an even integer, and an external memory which is connectedto said microprocessor through said external data bus and whose memoryarea is composed of a plurality of memory boundaries defined by n-bytesas one unit, each of said n-byte units having an upper half and a lowerhalf, wherein said data processor is provided with: bus-size switchingcircuitry for switching between first case of using said external databus in n-bytes width and a second case of using said external bus in n/2byte width when accessing said external memory; accessing circuitry for,in said first case, successively accessing a plurality of memoryboundaries, including a memory boundary where an address to be accessedexists, by wrapping around from said memory boundary where an address tobe accessed exits, and successively providing n-byte units derivedtherefrom to said external bus, and in said second case, successivelyaccessing a plurality of memory boundaries, including a memory boundarywhere an address to be accessed exists, by wrapping around from saidmemory boundary where an address to be accessed exists, and successivelyproviding n/2-byte units derived therefrom to said external bus; addressgenerating circuitry for generating a head address of said memoryboundary where said address to be accessed exists; and a bus interfacecircuit for (1) accessing successively the inside of said memory area inan order from the head address of addresses generated by said addressgenerating circuitry, and (2) in each of said first and second cases,accomplishing said accessing in an order which does not vary dependingon whether said address to be accessed is within the upper half of ann-byte unit beginning at the memory boundary where said address to beaccessed exists, or the lower half of said n-byte unit..Iaddend..Iadd.19. A data processing apparatus comprising: a processor;a data bus having a bus width; a first memory for storing blocks of datawhich is coupled to or within said processor; a second memory which iscoupled to said processor through said bus, said second memory having aplurality of addressable memory locations which are capable of beingorganized into blocks of data; a bus-sizer for switching between a stateof using a part of the bus width of said data bus for accessing saidsecond memory and a state of using all of said bus width for accessingsaid second memory; circuitry for, responsive to a signal representativeof a condition in which an operand desired by the processor is notstored in the first memory, (a) accessing a block in the second memorycontaining said operand through a series of accesses of memory locationssufficient to retrieve said block, (b) transmitting said block over saidbus through a series of successive transfers of data units over saidbus, said units having a first width in the case in which all of saidbus width of said data bus is used, and having a second width less thansaid first width in the case in which a part of the bus width of saiddata bus is used, and (c) storing said transmitted block in said firstmemory. .Iaddend..Iadd.20. The apparatus of claim 19 wherein saidprocessor comprises a microprocessor, and said first memory comprises acache memory. .Iaddend..Iadd.21. A method for accessing memory in a dataprocessing system including a microprocessor, a first memory for storingblocks of data, a data bus having an effective bus width selectablebetween a first width and a second width less than said first width, anda second memory which is connected to said microprocessor through saiddata bus, said second memory having a plurality of addressable memorylocations which are capable of being organized into blocks, and whichdefine a plurality of memory boundaries spaced by said first width, themethod comprising the steps of:selecting whether the effective bus widthof said data bus is to be said first width or said second width;generating a signal indicating that an operand desired by themicroprocessor is not present in said first memory; responsive to saidsignal, generating an address of a memory location within a block of thesecond memory which contains the operand; accessing said block through aseries of accesses of memory locations sufficient to retrieve saidblock; transmitting said block over said bus through a series ofsuccessive transfers of data units over said bus, said data units havinga width which is less than or equal to said selected width; if theeffective bus width is selected to be said first width, beginning saidtransmitting with a data unit beginning on one of said memory boundariesand containing at least part of said desired operand; if the effectivebus width is selected to be said second width, beginning saidtransmitting with a data unit beginning on one of said memory boundariesand wholly excluding said desired operand; and storing said transmittedblock in said first memory. .Iaddend..Iadd.22. A method for accessingmemory in a data processing system including a microprocessor, a firstmemory for storing blocks of data, a data bus having an effective buswidth selectable between a first width and a second width less then saidfirst width, ad a second memory which is connected to saidmicroprocessor through said data bus, said second memory having aplurality of addressable memory locations which are capable of beingorganized into blocks of data segments having said first width, themethod comprising the steps of: selecting whether the effective buswidth of said data bus is to be said first width or said second width;generating a signal indicating that an operand desired by themicroprocessor is not present in said first memory; responsive to saidsignal, generating an address of a memory location within a particulardata segment of a block of the second memory at which said operandbegins; accessing said block through a series of accesses of memorylocations sufficient to retrieve said block; transmitting said blockover said bus through a series of successive transfers of data unitsaver said bus, said data units having a width which is less than orequal to said selected width; when the effective bus width is either ofsaid first and second widths accomplishing said transmitting in an orderwhich does not vary depending on where the desired operand begins withinsaid particular segment having said first width; and storing saidtransmitted block in said first memory. .Iaddend..Iadd.23. A method ofaccessing a block of memory through a data bus in a data processingsystem including a microprocessor, cache memory coupled to or within themicroprocessor for storing blocks of data, an external data bus having aselectable width, and an external memory coupled to said microprocessorthrough said bus, comprising the steps of: selecting a width from aplurality of predetermined widths; sizing said bus to said selectedwidth; in response to a cache miss condition, accessing said block fromsaid external memory, and transmitting said block over said bus througha burst of successive transfers of data units, said data units having awidth which is less than or equal to said selected width; accomplishingsaid transmitting beginning with a data unit wholly excluding saiddesired operand; and updating said cache memory with said transmittedblock. .Iaddend..Iadd.24. A method for accessing memory in a dataprocessing system including a microprocessor, a first memory for storingblocks of data, a data bus having an effective bus width selectablebetween a first width and a second width less than said first width, anda second memory which is connected to said microprocessor through saiddata bus, said second memory having a plurality of addressable memorylocations which are capable of being organized into blocks of data, themethod comprising the steps of: selecting whether the effective buswidth of said data bus is to be said first width or said second width;generating a signal indicating that an operand desired by themicroprocessor is not present in said first memory; responsive to saidsignal, generating an address of address of a memory location within ablock of the second memory which contains the operand; accessing saidblock through a series of accesses of memory locations sufficient toretrieve said block; transmitting said block over said bus through aseries of successive transfers of data units over said bus, said dataunit having a width which is less or equal to said selected width; ifsaid effective width of said data bus is selected to be said firstwidth, accomplishing said transmitting beginning with a data unitcontaining at least in part the desired operand; if said effective widthsaid data bus is selected to be said second width, accomplishing saidtransmitting beginning with a data unit wholly excluding said desiredoperand; and storing said transmitted block in said first memory..Iaddend..Iadd.25. A method for accessing memory in a data processor,said data processor having a microprocessor, means for storing a blockof data, an external data bus having an effective bus width selectable,between n-bytes and n/2 bytes, wherein n is an even integer, and anexternal memory which is connected to said microprocessor through saidexternal data bus, said external memory having a plurality ofaddressable memory locations each having width of n-bytes and eachhaving upper half and a lower half, the method comprising the stepsof:selecting whether said effective bus width of said external data busis to be n-bytes, or n/2 bytes; generating an access request to access aspecific addressable memory location in said external memory; generatinga head address of a block of data to be accessed, wherein said headaddress is generated based on said specific addressable memory location;accessing said external memory, wherein said accessing is accomplishedin a series of accesses sufficient to retrieve a block of data;generating a bus transfer finishing signal upon completion of each ofsaid series of accesses; transferring said block of data through aninternal data bus said internal data bus, having a bus width equal ton-bytes; when the effective bus width is n-bytes and when the effectivebus width is n/2-bytes, storing said block of data, wherein said storingis accomplished in an order which does not vary depending upon whethersaid specific addressable memory location begins within the upper halfof an n-byte unit, or within the lower half of the n-byte unit; andtransferring said block of data to said means for storing..Iaddend..Iadd.26. A method for accessing memory in a data processor,said data processor having a microprocessor, means for storing a blockof data, an external data bus having an effective bus width selectablebetween n-bytes and n/2 bytes, wherein n is an even integer, and anexternal memory which is connected to said microprocessor through saidexternal data bus, said external memory having a plurality ofaddressable memory locations each having a width of n-bytes and eachhaving upper half and a lower half the method, comprising the steps of:selecting whether said effective bus width of said external data bus isto be n-bytes or n/2 bytes; generating an access request to access aspecific addressable memory location said external memory; generating ahead address of a block of data to be accessed, wherein said headaddress is generated based on said specific addressable memorylocations; accessing said external memory, wherein said accessing isaccomplished in a series of accesses sufficient to retrieve a block ofdata; generating a bus transfer finishing signal upon completion of eachof said series of accesses; transferring block of data through aninternal data bus, said internal data bus having a bus width equal ton-bytes; when the specific addressable memory location begins within theupper half of an n-byte unit, and when it begins within the lower halfof an n-byte unit storing said block of data, wherein said storing isaccomplished in a certain order if said external bus width is n-bytes,and is accomplished in the same order if said external bus width is n/2bytes; and transferring said block of data to said means for storing..Iaddend..Iadd.27. The method of claim 26 in which n is 8 and said blockof data is 256 bits wide. .Iaddend..Iadd.28. A method for accessingmemory in a data processing system including a microprocessor, a firstmemory for storing blocks of data, a data bus having an effective buswidth selectable between a first width and a second width less than saidfirst width, and a second memory which is connected to saidmicroprocessor through said data bus, said second memory having aplurality of addressable memory locations which are capable of beingorganized into blocks, the method comprising the steps of: selectingwhether the effective bus width of said data bus is to be said firstwidth or said second width; generating a signal indicating that anoperand desired by the microprocessor is not present in said firstmemory; responsive to said signal, generating an address of a memorylocation within a block of the second memory which contains the operand;accessing said block through a series of accesses of memory locationssufficient to retrieve said block; transmitting said block over said busthrough a series of successive transfers of data units over said bus,said data units having a width which is less than or equal to saidselected width; if said effective bus width is selected to be said firstwidth, providing said data units to an internal bus; if said effectivebus width is selected to be said second width, successively combiningselected ones of said data units into combined data units, and providingsaid combined data units to said internal bus; and storing saidtransmitted block in said first memory. .Iaddend..Iadd.29. A method ofaccessing a block of memory having a width and containing a desiredoperand through a data bus in a data processing system including amicroprocessor, a cache memory coupled to or within the microprocessorfor storing blocks of data, an external data bus having a selectablewidth, and an external memory coupled to said microprocessor throughsaid bus, comprising the steps of: selecting a width from a plurality ofpredetermined widths; sizing said bus to said selected width; inresponse to a cache miss condition, accessing said block from saidexternal memory, and transmitting said block over said bus through aburst of successive transfers of data units, said data units having awidth which is less than or equal to said selected width; successivelycombining selected ones of said data units into combined data units, andproviding said combined units to said internal bus; and updating saidcache memory with said transmitted block. .Iaddend..Iadd.30. A dataprocessor apparatus comprising: a processor; a data bus having a buswidth; a first memory for storing blocks of data which is coupled tosaid processor through an internal bus; a second memory which is coupledto said processor through said data bus, said second memory having aplurality of addressable memory locations which are capable of beingorganized into blocks of data; a bus-sizer for switching between a stateof using a part of the bus width of said data bus for accessing saidsecond memory and a state of using all of said bus width for accessingsaid second memory; circuitry for, responsive to a signal representativeof a condition in which an operand desired by the processor is notstored in the first memory, (a) accessing a block in the second memorycontaining said operand through a series of accesses of memory locationssufficient to retrieve said block, (b) transmitting said block over saidbus through a series of successive transfers of data units over saidbus, said units having a first width in the case in which all of saidbus width of said data bus is used, and having a second width less thansaid first width in the case in which a part of the bus width of saiddata bus is used, (c) if all of said bus width of said data bus is used,providing said data units to said internal bus, (d) if part of said buswidth of said data bus is used, successively combining selected ones ofsaid data units into combined units, and providing said combined unitsto said internal bus, and (e) storing said transmitted block in saidfirst memory. .Iaddend..Iadd.31. A data processor apparatus comprising:a processor; a data bus having a bus width; a first memory for storingblocks of data which is coupled to said processor through an internalbus; a second memory which is coupled to said processor through saiddata bus, said second memory having a plurality of addressable memorylocations which are capable of being organized into blocks of data; abus-sizer for switching between a state of using a part of the bus widthof said data bus for accessing said second memory and a state of usingall of said bus width for accessing said second memory; circuitry for,responsive to a signal representative of a condition in which an operanddesired by the processor is not stored in the first memory, (a)accessing a block in the second memory containing said operand through aseries of accesses of memory locations sufficient to retrieve saidblock, (b) transmitting said block over said bus through a series ofsuccessive transfers of data units over said bus, said data units havinga first width in the case in which all of said bus width of said databus is used, and having a second width less than said first width in thecase in which a part of the bus width of said data bus is used, (c) ifall of said bus width of said data bus is used, beginning saidtransmitting with a data unit containing at least in part said desiredoperand, (d) if part of said bus width of said data bus is used,beginning said transmitting with a data unit which may wholly excludesaid desired operand, and (e) storing said transmitted block in saidfirst memory. .Iaddend..Iadd.32. A data processor apparatus comprising:a processor; a data bus having a bus width; a first memory for storingblocks of data which is coupled to said processor through an internalbus; a second memory which is coupled to said processor through saiddata bus, said second memory having a plurality of addressable memorylocations which are capable of being organized into blocks of datadefining a plurality of memory boundaries spaced by a first width; abus-sizer for switching between a state of using a part of the bus widthof said data bus for accessing said second memory and a state of usingall of said bus width for accessing said second memory; circuitry for,responsive to a signal representative of a condition in which an operanddesired by the processor is not stored in the first memory, (a)accessing a block in the second memory containing said operand through aseries of accesses of memory locations sufficient to retrieve saidblock, (b) transmitting said block over said bus through a series ofsuccessive transfers of data units over said bus, said data units havingsaid first width in the case in which all of said bus width of said databus is used, and having a second width less than said first width in thecase in which a part of the bus width of said data bus is used, (c) ifall of said bus width of said data bus is used, beginning said transferswith a data unit beginning on one of said plurality of memory boundariesspaced by said first width, (d) if part of said bus width of said databus is used, also beginning said transfers with a data unit beginning onone of said plurality of memory boundaries, even if said data unitwholly excludes said desired operand, and (e) storing said transmittedblock in said first memory. .Iaddend..Iadd.33. A method for accessingmemory in a data processing system including a microprocessor, a firstmemory for storing blocks of data, a data bus having an effective buswidth selectable between a first width and a second width less than saidfirst width, and a second memory which is connected to saidmicroprocessor through said data bus, said second memory having aplurality of addressable memory locations which are capable of beingorganized into blocks of data, the method comprising the stepsof:selecting whether the effective bus width of said data bus is to besaid first width or said second width; generating a signal indicatingthat an operand desired by the microprocessor is not present in saidfirst memory; responsive to said signal, generating an address of amemory location within a block of the second memory which contains theoperand; accessing said block through a series of accesses of memorylocations sufficient to retrieve said block; transmitting said blockover said bus through a series of successive transfers of data unitsover said bus, said data units having a width which is less than orequal to said selected width; if said effective width of said data busis selected to be said first width, accomplishing said transmitting in acertain order beginning with a data unit containing at least in part thedesired operand; if said effective width of said data bus is selected tobe said second width, accomplishing said transmitting in the same orderbeginning with a data unit wholly excluding said desired operand; andstoring said transmitted block in said first memory. .Iaddend..Iadd.34.A data processor comprising a microprocessor, an external data bushaving a bus width, and an external memory which is connected to saidmicroprocessor, and which has a plurality of addressable memorylocations which are capable of being organized into blocks of datasegmented by memory boundaries spaced by a first width, wherein saiddata processor is provided with:bus-sizing means for switching between astate of using a part of the bus width of said external data bus and astate of using all of said bus width for accessing said external memory;accessing means for, responsive to a signal representative of acondition in which an operand desired by the processor is not stored inthe external memory, accessing said external memory successively byexecuting a predetermined number of external bus accesses as a set, anda bus interface circuit for receiving a request for an access start andstarting an external bus access to said external memory; and whereinsaid bus interface circuit, in response to a request for an access startwhen all of said bus width of said external data bus is used, generatesa single set of successive external bus accesses, and receivessuccessive data units over said external bus in response thereto, thedata units having said first width, beginning with a data unit on one ofsaid memory boundaries spaced by said first width, and when a part ofthe bus width of the external data bus is used, generates a plurality ofsets of successive external bus accesses, starts each set of successiveexternal bus accessing by generating addresses for the first externalbus access of each set of successive external bus accesses to accesssuccessively a memory area of the same size as in the case where all ofsaid bus width of said external data bus is used, and, for each set,receives successive data units over said external bus in responsethereto, the data units having a width less than said first width,beginning with a data unit on one of said memory boundaries spaced bysaid first width even when the data unit wholly excludes the desiredoperand. .Iaddend.